Group III-V compound semiconductors have intrinsically higher mobilities and other properties that are superior to silicon for particular functions, particularly optoelectronic functions as one example. Silicon remains the industry standard for the electronics industry standard, however, because the Group III-V materials are higher cost, involve more complex fabrication and are not as widely available as silicon.
A monolithic combination of Group III-V materials and silicon materials holds promise to provide the advantages of both material systems. Accordingly, research has turned toward the monolithic integration of Group III-V semiconductors with silicon. The different material systems have incompatibilities that make the integration less than straightforward.
Lattice and thermal expansion mismatch between the Group III-V semiconductors and silicon is one hurdle to overcome in the monolithic integration of the two material systems. Vertical structures address this difficulty by minimizing that contact area between the materials. A vertical Group III-V nanowire formed on a silicon layer, for example, has a very small contact area as compared to a planar integration typical in semiconductor fabrications where planar layers successively formed and patterned. The small contact area of a vertical structure minimizes the lattice and thermal expansion mismatch inherent to the different material systems.
Achieving the goal of forming vertical Group III-V structures on silicon has generally been accomplished with catalysts. Typically, a metal catalyst is used. For example, Au-catalyzed III-V nanowire growth on silicon via the vapor-liquid-solid mechanism has been proposed for Group III-V vertical nanowire growth on silicon. See, e.g., Martensson, T.; Svensson, C. P. T.; Wacaser, B. A.; Larsson, M. W.; Seifert, W.; Deppert, K.; Gustafsson, A.; Wallenberg, L. R.; and Samuelson, L., “Epitaxial III-V Nanowires on Silicon,” Nano Letters, 2004. 4(10): p. 1987-1990; Bakkers, E. P. A. M.; Borgstrom, M. T.; and Verheijen, M. A., “Epitaxial Growth of III-V Nanowires on Group IV Substrates,” Mrs Bulletin, 2007. 32(2): p. 117-122; Bao, X.-Y.; Soci, C.; Susac, D.; Bratvold, J.; Aplin, D. P. R.; Wei, W.; Chen, C.-Y.; Dayeh, S. A.; Kavanagh, K. L.; and Wang, D., “Heteroepitaxial Growth of Vertical GaAs Nanowires on Si (111) Substrates by Metal-Organic Chemical Vapor Deposition,”. Nano Lett., 2008. 8(11): p. 3755-3760 The nanowires formed by the Au catalyzed method exhibit large islands at their base. The Au is also known to incorporated into the nanowire itself. The presence of Au additionally can cause unwanted deep level traps in the silicon layer upon which the nanowires are formed.
A recently proposed method is growth with a self-assembled organic coating or SiO2 template mask. See, Tomioka, K.; Motohisa, J.; Hara, S.; and Fukui, T., “Control of InAs Nanowire Growth Directions on Si,” Nano Letters, 2008. 8(10): p. 3475-3480. This method requires an extra material coating and high temperature baking steps. Self-catalyzed growth of III-V nanowires on silicon is a simpler technique, but reported methods do not provide control over the orientation of the nanowires that form. See, Mattila, M.; Hakkarainen, T.; Lipsanen, H.; Jiang, H.; and Kauppinen, E. I., “Catalyst-Free Growth of In(As)P Nanowires on Silicon,” Applied Physics Letters, 2006. 89(6): p. 3; Jabeen, F.; Grillo, V.; Rubini, S.; and Martelli, F., “Self-catalyzed growth of GaAs nanowires on cleaved Si by molecular beam epitaxy,” Nanotechnology, 2008. 19(27): p. 275711.